| Item type |
デフォルトアイテムタイプ_（フル）(1) |
| 公開日 |
2023-03-18 |
| タイトル |
|
|
タイトル |
Mechanism of dynamic bias temperature instability in p- and nMOSFETs: The effect of pulse waveform |
|
言語 |
en |
| 作成者 |
Zhu, Shiyang
Nakajima, Anri
Ohashi, Takuo
Miyake, Hideharu
|
| アクセス権 |
|
|
アクセス権 |
open access |
|
アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 権利情報 |
|
|
権利情報 |
Copyright (c) 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
Bias temperature instability (BTI) |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
Direct-current current-voltage (DCIV) |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
Dynamic stress |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
Interface states |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
Interface trap generation |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
MOSFET |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
Reaction-diffusion (R-D) model |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
Reliability |
| 主題 |
|
|
主題Scheme |
NDC |
|
主題 |
540 |
| 内容記述 |
|
|
内容記述 |
The waveform effect on dynamic bias temperature instability (BTI) is systematically studied for both p- and nMOSFETs with ultrathin SiON gate dielectrics by using a modified direct-current current-voltage method to monitor the stress-induced interface trap density. Interface traps are generated at the inversion gate bias (negative for pMOSFETs and positive for nMOSFETs) and are partially recovered at the zero or accumulation gate bias. Devices under high-frequency bipolar stress exhibit a significant frequency-dependent degradation enhancement. Approximate analytical expressions of the interface trap generation for devices under the static, unipolar, or bipolar stress are derived in the framework of conventional reaction-diffusion (R-D) model and with an assumption that additional interface traps (N*it) are generated in each cycle of the dynamic stress. The additional interface trap generation is proposed to originate from the transient trapped carriers in the states at and/or near the SiO2/Si interface upon the gate voltage reversal from the accumulation bias to the inversion bias quickly, which may accelerate dissociation of Si-H bonds at the beginning of the stressing phase in each cycle. Hence, N*it depends on the interface-state density, the voltage at the relaxation (i.e., accumulation) bias, and the transition time of the stress waveform (the fall time for pMOSFETs and the rise time for nMOSFETs). The observed dynamic BTI behaviors can be perfectly explained by this modified R-D model. |
|
言語 |
en |
| 出版者 |
|
|
出版者 |
IEEE |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
|
|
資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
|
資源タイプ |
journal article |
| 出版タイプ |
|
|
出版タイプ |
VoR |
|
出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
| 関連情報 |
|
|
|
識別子タイプ |
DOI |
|
|
関連識別子 |
10.1109/TED.2006.877876 |
| 関連情報 |
|
|
|
識別子タイプ |
DOI |
|
|
関連識別子 |
http://dx.doi.org/10.1109/TED.2006.877876 |
| 収録物識別子 |
|
|
収録物識別子タイプ |
ISSN |
|
収録物識別子 |
0018-9383 |
| 収録物識別子 |
|
|
収録物識別子タイプ |
NCID |
|
収録物識別子 |
AA00667820 |
| 開始ページ |
|
|
開始ページ |
1805 |
| 書誌情報 |
IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices
巻 53,
号 8,
p. 1805-1814,
発行日 2006-08
|
| 旧ID |
15048 |
IEEETranElectDev_53_1805.pdf (1.3 MB)
