| Item type |
デフォルトアイテムタイプ_（フル）(1) |
| 公開日 |
2023-03-18 |
| タイトル |
|
|
タイトル |
Atomic layer-deposited Si-nitride/SiO2 stack gate dielectrics for future high-speed DRAM with enhanced reliability |
|
言語 |
en |
| 作成者 |
Nakajima, Anri
Ohashi, Takuo
Zhu, Shiyang
Yokoyama, Shigeyuki
Michimata, Shigetomi
Miyake, Hideharu
|
| アクセス権 |
|
|
アクセス権 |
open access |
|
アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 権利情報 |
|
|
権利情報 |
Copyright (c) 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
Atomic layer deposition (ALD) |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
DRAM |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
MOSFET |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
Si nitride |
| 主題 |
|
|
主題Scheme |
Other |
|
主題 |
Stack gate dielectrics |
| 主題 |
|
|
主題Scheme |
NDC |
|
主題 |
540 |
| 内容記述 |
|
|
内容記述 |
Atomic layer-deposited (ALD) Si-nitride/SiO"2 stack gate dielectrics were applied to high-performance transistors for future scaled DRAMs. The stack gate dielectrics of the peripheral pMOS transistors excellently suppress boron penetration. ALD stack gate dielectrics exhibit only slightly worse negative-bias temperature instability (NBTI) characteristics than pure gate oxide. Enhanced reliability in NBTI was achieved compared with that of plasma-nitrided gate SiO"2. Memory-cell (MC) nMOS transistors with ALD stack gate dielectrics show slightly smaller junction leakage than those with plasma-nitrided gate SiO"2 in a high-drain-voltage region, and have identical junction leakage characteristics to transistors with pure gate oxide. MCs having transistors with ALD stack gate dielectrics and those with pure gate oxide have the identical retention-time distribution. Taking the identical hole mobility for the transistors with ALD stack gate dielectrics to that for the transistors with pure gate oxide both before and after hot carrier injection (previously reported) into account, the ALD stack dielectrics are a promising candidate for the gate dielectrics of future high-speed, reliable DRAMs. |
|
言語 |
en |
| 出版者 |
|
|
出版者 |
IEEE |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
|
|
資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
|
資源タイプ |
journal article |
| 出版タイプ |
|
|
出版タイプ |
VoR |
|
出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
| 関連情報 |
|
|
|
識別子タイプ |
DOI |
|
|
関連識別子 |
10.1109/LED.2005.851822 |
| 関連情報 |
|
|
|
識別子タイプ |
DOI |
|
|
関連識別子 |
http://dx.doi.org/10.1109/LED.2005.851822 |
| 収録物識別子 |
|
|
収録物識別子タイプ |
ISSN |
|
収録物識別子 |
0741-3106 |
| 収録物識別子 |
|
|
収録物識別子タイプ |
NCID |
|
収録物識別子 |
AA00231428 |
| 開始ページ |
|
|
開始ページ |
538 |
| 書誌情報 |
IEEE Electron Device Letters
IEEE Electron Device Letters
巻 26,
号 8,
p. 538-540,
発行日 2005-08
|
| 旧ID |
15050 |
IEEEElectDevLett_26_538.pdf (115.3 KB)
