| Item type |
デフォルトアイテムタイプ_（フル）(1) |
| 公開日 |
2023-03-18 |
| タイトル |
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タイトル |
Low-temperature formation of silicon nitride gate dielectrics by atomic-layer deposition |
|
言語 |
en |
| 作成者 |
Nakajima, Anri
Yoshimoto, Takashi
Kidera, Toshirou
Yokoyama, Shin
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| アクセス権 |
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アクセス権 |
open access |
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アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 権利情報 |
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権利情報 |
Copyright (c) 2001 American Institute of Physics. |
| 内容記述 |
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内容記述 |
Thin (equivalent oxide thickness Teq of 2.4 nm) silicon nitride layers were deposited on Si substrates by an atomic-layer-deposition (ALD) technique at low temperatures (<550°C). The interface state density at the ALD silicon nitride/Si-substrate interface was almost the same as that of the gate SiO2. No hysteresis was observed in the gate capacitance-gate voltage characteristics. The gate leakage current was the level comparable with that through SiO2 of the same Teq. The conduction mechanism of the leakage current was investigated and was found to be the direct tunneling. The ALD technique allows us to fabricate an extremely thin, very uniform silicon nitride layer with atomic-scale control for the near-future gate dielectrics. |
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言語 |
en |
| 出版者 |
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出版者 |
American Institute of Physics |
| 言語 |
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言語 |
eng |
| 資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
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資源タイプ |
journal article |
| 出版タイプ |
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出版タイプ |
VoR |
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出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
| 関連情報 |
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識別子タイプ |
DOI |
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関連識別子 |
10.1063/1.1388026 |
| 関連情報 |
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識別子タイプ |
DOI |
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関連識別子 |
http://dx.doi.org/10.1063/1.1388026 |
| 収録物識別子 |
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収録物識別子タイプ |
ISSN |
|
収録物識別子 |
0003-6951 |
| 収録物識別子 |
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収録物識別子タイプ |
NCID |
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収録物識別子 |
AA00543431 |
| 開始ページ |
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開始ページ |
665 |
| 書誌情報 |
Applied Physics Letters
Applied Physics Letters
巻 79,
号 5,
p. 665-667,
発行日 2001-07-30
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| 旧ID |
18586 |
ApplPhysLett_79_665.pdf (82.0 KB)
