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oai:hiroshima.repo.nii.ac.jp:02006996 2025-02-21T08:57:12Z 1730444907710

Enhancement of BTI degradation in pMOSFETs under high-frequency bipolar gate bias Zhu, Shiyang Zhu Shiyang Nakajima, Anri Nakajima Anri Ohashi, Takuo Ohashi Takuo Miyake, Hideharu Miyake Hideharu open access Copyright (c) 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Dynamic stress Negative bias temperature instability (NBTI) pMOSFETs Recombination Ultrathin gate oxide 540 Negative bias temperature (NBT) instability of p-MOSFETs with ultrathin SiON gate dielectric has been investigated under various gate bias configurations. The NBT-induced interface trap density (ΔNit) under unipolar bias is essentially lower than that under static bias, and is almost independent of the stress frequency up to 10 MHz. On the contrary, ΔNit under bipolar pulsed bias of frequency larger than about 10 kHz is significantly enhanced and exhibits a strong frequency dependence, which has faster generation rate and smaller activation energy as compared to other stress configurations. The degradation enhancement is attributed to the energy to be contributed by the recombination of trapped electrons and free holes upon the silicon surface potential reversal from accumulation to inversion. 2005-06 eng journal article VoR https://hiroshima.repo.nii.ac.jp/records/2006996 10.1109/LED.2005.848075 http://dx.doi.org/10.1109/LED.2005.848075 0741-3106 AA00231428 IEEE Electron Device Letters IEEE Electron Device Letters 26 6 387 387 389 https://hiroshima.repo.nii.ac.jp/record/2006996/files/IEEEElectDevLett_26_387.pdf 135.8 KB